FRANKENCHIP - This will change how computing is done

Also, without reading the article, are we talking about extending the ISA to include instructions for accessing this FPGA? Curious as to the technical implementation details.

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Also, without reading the article, are we talking about extending the ISA to include instructions for accessing this FPGA? Curious as to the technical implementation details.

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I dunno. That's a good question. I would think they would have to.


I've been doing some more reading and the FPGA companies themselves have been making FPGA+CPUs for a while now.



It may turn out you don't need the CPU at all. There are already several open source CPUs that you can download and install to an FPGA. Think about the implications - rather than buying a particular CPU, you'd just buy an FPGA - and the software required to program a CPU into the chip - and upgrades to the CPU could be done via software!

Whatever FPGA gates you had leftever could be used for specialized hardware or for additional cores - or for a GPU. The same FPGA could be tailored to gamers, science & engineering, data base management - etc.


I think it would be interesting to see how many OISC's could be crammed into one FPGA.

These guys made a 1,000 core CPU with an FPGA:


LINK


They processed mpegs with it 20x faster.

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Any decent EE/CPE degree has been requiring VHDL classes for 20 years. Most universities call it advanced digital logic.

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Of course - isn't that basically what most EE's do these days anyway?

I'm talking about software engineers. These guys (me for instance) are going to have to learn to program hardware. At least the ones with apps that require top performance. And I see the EE guys as being competitors - I think its a lot easier for an EE to learn C++ than it is for a CS to learn Verilog.

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FPGAs are making a comeback to provide specialization speed increases as they just can't add more cores anymore. It's like math co-processers back in the day to give floating point arithmetic.

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I'm loving it every time I read about these things. I've been doing HPC for years and I have every now and then heard of people using ASICs or FPGAs to accelerate something - but now FPGA clusters are becoming more and more common. They will ultimately blow GPUs away, I think, because you can always program an FPGA to act like a GPU.


The FPGA+CPU on the same chip will make it even more useful. The FPGA has direct access to the CPU's cache - this means you can use the FPGA to create custom caching algorithms.




The cool thing about Verilog from my POV is that it is dataflow oriented. Most of the high performance stuff I write is best expressed as a dataflow (from one short lived fine grained thread to the next).

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This is the nerdiest active thread currently on the Tech Board.

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That's a shame if you think about it.

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Once we hit the theoretical physical limit of a gate length (a single atom or whatever), where do we go from there?

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parallelism is the answer. On all levels.

The FPGA - essentially - is a way to achieve extremely fine grained parallelism. But parallelism will have to be exploited at all levels to realize full performance potential. The Intel Phis - for instance - ~70 cores on one chip ( and I think each is 4 threads - so 280 threads).

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The thing is performance isn't really that relevant right now. for most applications, current hardware provides more than enough processing power for applications.

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This is why I qualified it as being crucial for performance critical programming.


I would point out - however - that I think the landscape is changing in terms of what business's will demand in software. Now that HPC is available in the Cloud - small and medium sized businesses can make use of it without having to overcome the hurdle of buying and maintaining their own machine.

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Even with big data the barrier is often memory addressing more so than processing speed.

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You are right on the point that memory bandwidth constitutes a huge hurdle. I think there is still room for improvement in terms of algorithms, though.

Caching for instance is hardly ever used in the most optimal way. FPGA's may be able to help with custom caching (I'm just speculating - I haven't read anything that says they can).