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re: FRANKENCHIP - This will change how computing is done

Posted on 7/12/14 at 10:42 am to
Posted by UltimaParadox
Huntsville
Member since Nov 2008
40900 posts
Posted on 7/12/14 at 10:42 am to
Any decent EE/CPE degree has been requiring VHDL classes for 20 years. Most universities call it advanced digital logic.

FPGAs are making a comeback to provide specialization speed increases as they just can't add more cores anymore. It's like math co-processers back in the day to give floating point arithmetic.
Posted by CP3
Baton Rouge
Member since Sep 2009
7418 posts
Posted on 7/12/14 at 10:51 am to
Yup. We had verilog in digital logic I & II at Lsu which is required for both computer and electrical engineering.
Posted by SpidermanTUba
my house
Member since May 2004
36128 posts
Posted on 7/17/14 at 11:25 am to
quote:

Any decent EE/CPE degree has been requiring VHDL classes for 20 years. Most universities call it advanced digital logic.



Of course - isn't that basically what most EE's do these days anyway?

I'm talking about software engineers. These guys (me for instance) are going to have to learn to program hardware. At least the ones with apps that require top performance. And I see the EE guys as being competitors - I think its a lot easier for an EE to learn C++ than it is for a CS to learn Verilog.

quote:


FPGAs are making a comeback to provide specialization speed increases as they just can't add more cores anymore. It's like math co-processers back in the day to give floating point arithmetic.


I'm loving it every time I read about these things. I've been doing HPC for years and I have every now and then heard of people using ASICs or FPGAs to accelerate something - but now FPGA clusters are becoming more and more common. They will ultimately blow GPUs away, I think, because you can always program an FPGA to act like a GPU.


The FPGA+CPU on the same chip will make it even more useful. The FPGA has direct access to the CPU's cache - this means you can use the FPGA to create custom caching algorithms.




The cool thing about Verilog from my POV is that it is dataflow oriented. Most of the high performance stuff I write is best expressed as a dataflow (from one short lived fine grained thread to the next).
This post was edited on 7/17/14 at 11:28 am
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